Chris Myers
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b11268ec9c
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Updated to suppot later Java versions
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2024-11-26 20:27:58 -07:00 |
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Chris Myers
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fe229873e7
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Updated pom files
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2021-06-24 19:34:08 -06:00 |
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Chris Myers
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24423a0826
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Remove JSBML dependency
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2020-09-10 16:44:07 -06:00 |
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Chris Myers
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515c7634a2
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Remove objects with same displayId before creating new
Fix run deadlock on errors
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2020-05-10 13:37:36 -06:00 |
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Tramy Nguyen
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522a74d5e2
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removed old technology mapping classes related
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2019-11-24 18:13:09 -05:00 |
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Tramy Nguyen
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2d61736103
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resolved merge conflict for verilogCompiler to master branch
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2019-11-24 17:56:26 -05:00 |
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Tramy Nguyen
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f9886bb7cf
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- removed node preselection feature from GUI
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2019-11-24 16:45:57 -05:00 |
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Tramy Nguyen
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5458c21eb7
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successful run for yosys but not sbol tech. map
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2019-09-27 12:56:15 -06:00 |
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Tramy Nguyen
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5600b73925
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running atacs without successfully running yosys
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2019-09-26 15:59:30 -06:00 |
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Tramy Nguyen
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e3fb409ec2
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load verilog synthesis property
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2019-09-25 13:26:16 -06:00 |
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Tramy Nguyen
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70e91ff1c5
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add verilog file to project tree
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2019-09-16 16:22:14 -06:00 |
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Tramy Nguyen
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50ad8f615a
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ran examples for sequential tech. map
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2019-09-09 11:38:25 -06:00 |
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Tramy Nguyen
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687680a0d8
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techmap solution revision for greedy and exhaustive pt. 2
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2019-08-19 02:10:45 -06:00 |
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Tramy Nguyen
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37d4545b6d
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tech map non recursion for exhaustive and greedy
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2019-08-18 12:16:34 -06:00 |
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Tramy Nguyen
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0b4c8b0273
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filter example files
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2019-08-07 23:20:34 -06:00 |
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Tramy Nguyen
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dbe40b6d3a
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technology mapping tested for covering
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2019-08-07 23:20:07 -06:00 |
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Tramy Nguyen
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7f978c11cb
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perform tech. map cover with feedback
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2019-06-12 00:55:56 -06:00 |
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Tramy Nguyen
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4f37244523
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Merge branch 'master' of
https://github.com/MyersResearchGroup/iBioSim.git into verilogCompiler
Conflicts:
gui/src/main/java/edu/utah/ece/async/ibiosim/gui/Gui.java
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2019-04-23 17:28:24 -06:00 |
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Chris Myers
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b7ab474bd2
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Update DNA to DNA_REGION, RNA to RNA_REGION, update jsbml
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2019-04-20 17:29:35 -06:00 |
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Tramy Nguyen
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6f548c13a3
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Test decomposed gates
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2019-04-18 01:55:28 -06:00 |
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Tramy Nguyen
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bf8ae50f9a
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gate identifier revised
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2019-04-08 19:02:47 -06:00 |
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Tramy Nguyen
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6caf6a427c
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fixed decomposed specification
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2019-04-06 22:06:19 -06:00 |
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Tramy Nguyen
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d907c6f28e
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fix yosys error
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2019-02-09 17:47:40 -07:00 |
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Tramy Nguyen
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33677d8612
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support sbml delay string and real values
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2019-02-05 17:03:22 -07:00 |
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Tramy Nguyen
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abc452161e
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support gate generation
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2019-01-24 18:37:50 -07:00 |
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Tramy Nguyen
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56db09039e
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test cases for replacement and replacedBy
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2019-01-16 22:04:04 -07:00 |
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Tramy Nguyen
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2111d56e9c
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support replacedBy and replacement for verilog2sbml
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2019-01-15 16:43:30 -07:00 |
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Tramy Nguyen
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5da84b3f73
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test cases for sbol tech map
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2019-01-13 21:36:10 -07:00 |
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Tramy Nguyen
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86167355a8
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more tests for sbol tech. map
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2019-01-09 15:06:25 -07:00 |
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Tramy Nguyen
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da2b475326
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sbol tech. map test case
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2019-01-07 18:02:36 -07:00 |
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Tramy Nguyen
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42ab39cbc0
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remaining changes for supporting urandom_range
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2019-01-06 21:14:13 -07:00 |
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Tramy Nguyen
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569284876d
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support urandom_range
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2019-01-06 21:13:37 -07:00 |
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Tramy Nguyen
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ada705e262
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test gate generator
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2019-01-04 15:20:04 -07:00 |
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Tramy Nguyen
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f2c91bc947
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test sbol create copy
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2019-01-04 15:13:27 -07:00 |
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Tramy Nguyen
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7704d7d15a
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support verilog import to workspace
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2018-12-27 19:47:33 -07:00 |
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Tramy Nguyen
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6b65c00e0c
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update failing test cases
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2018-12-26 23:40:21 -07:00 |
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Tramy Nguyen
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90cd29f671
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more SBOL tests for VerilogCompiler
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2018-12-26 17:13:59 -07:00 |
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Tramy Nguyen
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83f5e7b36e
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test1 for verilog to sbol hierarchy
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2018-12-26 16:09:39 -07:00 |
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Tramy Nguyen
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ef54a6b481
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rename testing classes
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2018-12-26 13:01:26 -07:00 |
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Tramy Nguyen
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24f6134116
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handle feedback for subcircuits for verilog compiler to sbol
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2018-12-25 21:38:05 -07:00 |
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Tramy Nguyen
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fe18c7376b
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add subcircuit for sbol
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2018-12-25 18:14:10 -07:00 |
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Tramy Nguyen
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224756adba
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support hierarchy for verilog to sbol
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2018-12-24 22:15:06 -07:00 |
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Tramy Nguyen
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80d1566fb7
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update test cases
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2018-12-15 17:58:53 -07:00 |
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Tramy Nguyen
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ff4a513692
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test cases for verilog to sbol
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2018-12-01 18:09:39 -07:00 |
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Tramy Nguyen
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808aa14e9c
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fixed NOT parsed into SBOL
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2018-12-01 14:59:23 -07:00 |
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Tramy Nguyen
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fa72009457
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cleaned up unused methods
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2018-11-29 19:30:57 -07:00 |
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Tramy Nguyen
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ca934a4106
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fixed SBOL NOR gates for decomposition
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2018-11-29 19:10:13 -07:00 |
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Tramy Nguyen
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280388b9fc
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code clean up for outputting data for compiler
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2018-11-21 14:21:57 -07:00 |
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Tramy Nguyen
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45322c479f
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modified how output data should be generated
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2018-11-13 18:21:05 -07:00 |
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Tramy Nguyen
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fafb29ffe0
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added test cases for verilog compiler
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2018-11-12 16:22:36 -07:00 |
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