36 lines
1.8 KiB
Text
36 lines
1.8 KiB
Text
Now generating atomic gate implementations.
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Verbose mode now turned ON.
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Using DBMs to obtain state graphs from LHPNs.
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Loading LPN: /Users/tramyn/Desktop/caseStudies/filter.lpn
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Expanding design: Making 0 implicit places explicit.
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Performing Petri net transformations.
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Initial net size: places=42 trans=42 rules=84
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Expanding design: Making 0 implicit places explicit.
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Temporarily removing ordering rules.
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places=42 trans=42 rules=84
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Adding ordering rules back in.
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Done performing Petri net transformations.
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Final net size: places=42 trans=42 rules=84
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Total transformation time: 0.000834
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places=42 trans=42 rules=84
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Using single-cube algorithm for synthesis.
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Finding reduced state graph; storing to: /Users/tramyn/Desktop/caseStudies/filter.rsg
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Zones: 62
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States: 62
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CPU Time: 0.02
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Real Time: 0.00726581
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memory: max=3.10031 Mb inuse=2.4561 Mb allocated=29.2383 Mb
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Projecting out dummy transitions and storing to: /Users/tramyn/Desktop/caseStudies/filter.rsg
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Checking output semi-modularity ... output semi-modular
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Checking CSC ... complete state coded
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Finding regions and storing to: /Users/tramyn/Desktop/caseStudies/filter.es
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Finding conflicts and storing context rule tables to: /Users/tramyn/Desktop/caseStudies/filter.crt
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Finding covers and storing to: /Users/tramyn/Desktop/caseStudies/filter.cov
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EXCEPTION: Storing unresolved conflicts to: /Users/tramyn/Desktop/caseStudies/filter.err
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Resolving remaining covers and storing to: /Users/tramyn/Desktop/caseStudies/filter.cov
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Storing production rules to: /Users/tramyn/Desktop/caseStudies/filter.prs
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Synthesis succeeded with area = 9 literals 18 transistors
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Storing simulation file to: /Users/tramyn/Desktop/caseStudies/filter.v
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DOT now being used for display and print routines.
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Generating dot file for net: /Users/tramyn/Desktop/caseStudies/filter.dot
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Executing command: shownet /Users/tramyn/Desktop/caseStudies/filter &
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