add verilog file to project tree

This commit is contained in:
Tramy Nguyen 2019-09-16 16:22:14 -06:00
parent 50ad8f615a
commit 70e91ff1c5
9 changed files with 1345 additions and 265 deletions

View file

@ -202,7 +202,9 @@ public class GlobalConstants {
public static final String SBOL_SYNTH_EXHAUST_BB = "Exact Branch and Bound";
public static final String SBOL_SYNTH_METHOD_DEFAULT = SBOL_SYNTH_EXHAUST_BB;
public static final String SBOL_SYNTH_GREEDY_BB = "Greedy Branch and Bound";
public static final String SBOL_SYNTH_STRUCTURAL_METHODS = SBOL_SYNTH_EXHAUST_BB + "," + SBOL_SYNTH_GREEDY_BB;
public static final String SBOL_SYNTH_GREEDY = "Greedy";
public static final String SBOL_SYNTH_EXHAUSTIVE = "Exhaustive";
public static final String SBOL_SYNTH_STRUCTURAL_METHODS = SBOL_SYNTH_EXHAUST_BB + "," + SBOL_SYNTH_GREEDY_BB + "," + SBOL_SYNTH_GREEDY + "," + SBOL_SYNTH_EXHAUSTIVE;
public static final String SBOL_SYNTH_NUM_SOLNS_PROPERTY = "synthesis.numsolutions";
public static final String SBOL_SYNTH_NUM_SOLNS_PREFERENCE = "biosim." + SBOL_SYNTH_NUM_SOLNS_PROPERTY;