diff --git a/docs/SynBioTutorial/GeneticToggle/GeneticToggle.xml b/docs/SynBioTutorial/GeneticToggle/GeneticToggle.xml
index 16244f114..7fa663791 100644
--- a/docs/SynBioTutorial/GeneticToggle/GeneticToggle.xml
+++ b/docs/SynBioTutorial/GeneticToggle/GeneticToggle.xml
@@ -1,6 +1,6 @@
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-
\ No newline at end of file
+
diff --git a/docs/SynBioTutorial/GeneticToggleFull.xml b/docs/SynBioTutorial/GeneticToggleFull.xml
index da18a690b..74b5210d5 100644
--- a/docs/SynBioTutorial/GeneticToggleFull.xml
+++ b/docs/SynBioTutorial/GeneticToggleFull.xml
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\ No newline at end of file
+
diff --git a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBMLToLPN.java b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBMLToLPN.java
index c7ea5b2b9..d61c2d2c6 100644
--- a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBMLToLPN.java
+++ b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBMLToLPN.java
@@ -40,7 +40,7 @@ public class SBMLToLPN {
private Set places;
private ArrayList eventAssignmentBooleans;
private ASTNode ignoreNode = new ASTNode(Type.CONSTANT_TRUE);
-
+
/**
* The SBML to LPN constructor needed to setup the necessary variables before running conversion.
* @param tbWrapper: The SBML testbench of the modeling circuit. Set this parameter to null if the SBML document has no external ports to convert.
@@ -58,15 +58,14 @@ public class SBMLToLPN {
this.ignoreVariables = new HashSet<>();
this.eventAssignmentBooleans = new ArrayList<>();
}
-
-
+
+
/**
* Convert SBML to LPN.
* @return The LPN model
*/
public LPN convert() {
lpn = new LPN();
-
convertSBMLParameters();
addTransitions();
convertPorts();
@@ -74,7 +73,7 @@ public class SBMLToLPN {
return lpn;
}
-
+
/**
* Convert the given SBML document to an LPN model.
* @param tbWrapper
@@ -86,31 +85,28 @@ public class SBMLToLPN {
SBMLToLPN converter = new SBMLToLPN(tbWrapper, impWrapper, sbmlDocument);
return converter.convert();
}
-
private void convertPorts() {
- Model model = sbmlDocument.getModel();
Model tbModel = tbWrapper.getModel();
- CompModelPlugin modelPlugin = (CompModelPlugin) impWrapper.getModel().getPlugin("comp");
-
+ CompModelPlugin impModelPlugin = (CompModelPlugin) impWrapper.getModel().getPlugin("comp");
boolean isOutput = false;
boolean isInput = false;
- for(Parameter parameter : model.getListOfParameters()) {
+
+ for(Parameter parameter : sbmlDocument.getModel().getListOfParameters()) {
isOutput = false;
isInput = false;
- //Go over all parameters of flat model that are marked as booleans
+
if(parameter.getSBOTerm() == 602) {
- String id = parameter.getId();
- if(!ignoreVariables.contains(id)) {
- Parameter tbParameter = tbModel.getParameter(id);
+ String p_id = parameter.getId();
+ if(!ignoreVariables.contains(p_id)) {
+ Parameter tbParameter = tbModel.getParameter(p_id);
if(tbParameter != null) {
- CompSBasePlugin plugin = (CompSBasePlugin) tbParameter.getPlugin("comp");
- if(plugin != null) {
- for (ReplacedElement replacement : plugin.getListOfReplacedElements()) {
- String submoduleRefName = tbWrapper.getSubmoduleReferences().get(replacement.getSubmodelRef());
- if(submoduleRefName != null && impWrapper.getModel().getId().equals(submoduleRefName)) {
+ CompSBasePlugin tbPlugin = (CompSBasePlugin) tbParameter.getPlugin("comp");
+ if(tbPlugin != null) {
+ for (ReplacedElement replacement : tbPlugin.getListOfReplacedElements()) {
+ if(containSubmodelRef(replacement.getSubmodelRef())) {
String portRef = replacement.getPortRef();
- Port port = modelPlugin.getPort(portRef);
+ Port port = impModelPlugin.getPort(portRef);
if(port.getSBOTerm() == 601) {
isOutput = true;
break;
@@ -121,22 +117,45 @@ public class SBMLToLPN {
}
}
}
+ if(tbPlugin.isSetReplacedBy()) {
+ ReplacedBy replaceBy = tbPlugin.getReplacedBy();
+ if(containSubmodelRef(replaceBy.getSubmodelRef())) {
+ String portRef = replaceBy.getPortRef();
+ Port port = impModelPlugin.getPort(portRef);
+ if(port.getSBOTerm() == 601) {
+ isOutput = true;
+
+ }
+ else if(port.getSBOTerm() == 600) {
+ isInput = true;
+
+ }
+ }
+ }
}
}
if(isOutput) {
- lpn.addOutput(id, "false");
- }
- else if(isInput){
- lpn.addInput(id, "false");
+ lpn.addOutput(p_id, "false");
+ }
+ else if(isInput) {
+ lpn.addInput(p_id, "false");
}
else {
- lpn.addBoolean(id, "false");
+ lpn.addBoolean(p_id, "false");
}
}
}
}
}
+ private boolean containSubmodelRef(String submodelRef) {
+ String submoduleRefName = tbWrapper.getSubmoduleReferences().get(submodelRef);
+ if(submoduleRefName != null && impWrapper.getModel().getId().equals(submoduleRefName)) {
+ return true;
+ }
+ return false;
+ }
+
private void convertSBMLParameters() {
List parameters = sbmlDocument.getModel().getListOfParameters();
for(Parameter param : parameters) {
@@ -188,7 +207,7 @@ public class SBMLToLPN {
}
}
lpn.addTransition(event.getId());
-
+
}
}
@@ -218,7 +237,7 @@ public class SBMLToLPN {
lpn.addBoolAssign(event.getId(), variable, convertSBMLASTNode(assignment));
}
}
-
+
}
}
@@ -231,15 +250,15 @@ public class SBMLToLPN {
}
}
-
+
private ASTNode removePresetFromASTNode(ASTNode math) {
ASTNode clone = math.clone();
Queue queue = new LinkedList<>();
queue.add(clone);
-
+
while(!queue.isEmpty()) {
ASTNode node = queue.poll();
-
+
if(node.getType() == ASTNode.Type.RELATIONAL_EQ) {
if(node.getLeftChild().isName()) {
if(places.contains(node.getLeftChild().getName())) {
@@ -252,7 +271,7 @@ public class SBMLToLPN {
return ignoreNode;
}
}
-
+
for(ASTNode child : node.getListOfNodes()) {
queue.add(child);
}
@@ -261,8 +280,8 @@ public class SBMLToLPN {
return clone.getChild(0);
}
return clone;
-
-
+
+
}
private String convertSBMLASTNode(ASTNode mathNode) {
diff --git a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogCompiler.java b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogCompiler.java
index c43ba9c28..c578a3171 100644
--- a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogCompiler.java
+++ b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogCompiler.java
@@ -74,7 +74,6 @@ public class VerilogCompiler {
*/
public void parseVerilog() throws XMLStreamException, IOException, BioSimException {
for(Source_textContext vFile : this.stcList) {
-
VerilogParser v = new VerilogParser();
ParseTreeWalker.DEFAULT.walk(v, vFile);
@@ -95,21 +94,21 @@ public class VerilogCompiler {
}
public boolean containsSBMLData() {
- return this.vmoduleToSBML.isEmpty()? false : true;
+ return this.vmoduleToSBML.isEmpty();
}
public boolean containsSBOLData() {
- return this.vmoduleToSBOL.isEmpty()? false : true;
+ return this.vmoduleToSBOL.isEmpty();
}
- public void generateSBOL(boolean generateFlatModel, VerilogModule verilogModule) throws SBOLException, SBOLValidationException, ParseException, VerilogCompilerException {
+ private void generateSBOL(boolean generateFlatModel, VerilogModule verilogModule) throws SBOLException, SBOLValidationException, ParseException, VerilogCompilerException {
VerilogToSBOL v2sbol_conv = new VerilogToSBOL(generateFlatModel);
WrappedSBOL sbolData = v2sbol_conv.convertVerilog2SBOL(verilogModule);
this.vmoduleToSBOL.put(verilogModule.getModuleId(), sbolData);
}
- public void generateSBML(VerilogModule verilogModule) throws ParseException {
+ private void generateSBML(VerilogModule verilogModule) throws ParseException {
VerilogToSBML v2sbml = null;
if(verilogModule.getNumSubmodules() > 0) {
Map referredModules = new HashMap<>();
@@ -128,35 +127,49 @@ public class VerilogCompiler {
this.vmoduleToSBML.put(verilogModuleId, sbmlModel);
}
-
- public SBMLDocument flattenSBML(String outputDirectory, String fileFullPath) throws BioSimException, XMLStreamException, IOException{
- //Flatten the SBML models and then export to the same directory
- BioModel sbmlDoc = new BioModel(outputDirectory);
- if(fileFullPath == null) {
- throw new FileNotFoundException("fileFullPath was not provided to perform SBML flattening.");
+
+ /**
+ * Perform flattening on the verilog module with the given verilogModuleId and all its submodules that were compiled to SBML.
+ * @param verilogModuleId: The id to locate the verilog module when flattening is performed.
+ * @param outputDirectory: The output directory where the hierarchical SBML models will be exported to.
+ * @return An SBMLDocument with all of the merged contents.
+ * @throws BioSimException
+ * @throws XMLStreamException
+ * @throws IOException
+ */
+ public SBMLDocument flattenSBML(String verilogModuleId, String outputDirectory) throws BioSimException, XMLStreamException, IOException{
+ if(verilogModuleId == null || verilogModuleId.isEmpty()) {
+ throw new FileNotFoundException("The given verilogModuleId was not provided to perform SBML flattening.");
}
+ //iBioSim's flattening method will not perform flattening if the hierarchical SBML models are not exported into a file.
+ WrappedSBML tbWrapper = getSBMLWrapper(verilogModuleId);
+ String hierModelFullPath = outputDirectory + File.separator + verilogModuleId + ".xml";
+ exportSBML(tbWrapper.getSBMLDocument(), hierModelFullPath);
+
+ for(VerilogModuleInstance submodule : verilogModules.get(verilogModuleId).getSubmodules()) {
+ String refModule = submodule.getModuleReference();
+ WrappedSBML sbmlModel = getSBMLWrapper(submodule.getModuleReference());
+ exportSBML(sbmlModel.getSBMLDocument(), outputDirectory + File.separator + refModule + ".xml");
+ }
+
+ //Flatten the SBML models and then export to the same directory
+ BioModel sbmlDoc = new BioModel(outputDirectory);
+
//Loading the testbench file will also load the implementation file as well since externalModelDefinition is used.
- boolean isDocumentLoaded = sbmlDoc.load(fileFullPath);
+ boolean isDocumentLoaded = sbmlDoc.load(hierModelFullPath);
if(!isDocumentLoaded) {
- throw new BioSimException("Unable to perform flattening for the following SBML file " + fileFullPath, "Error Flattening SBML Files");
+ throw new BioSimException("Unable to perform flattening for the following SBML file " + hierModelFullPath, "Error Flattening SBML Files");
}
SBMLDocument flattenDoc = sbmlDoc.flattenModel(true);
return flattenDoc;
}
public void generateLPN(String implementationModuleId, String testbenchModuleId, String outputDirectory) throws SBMLException, XMLStreamException, ParseException, BioSimException, IOException {
- //iBioSim's flattening method will not perform flattening if the hierarchical SBML models are not exported into a file.
- exportSBML(getMappedSBMLWrapper(), outputDirectory);
- String hierModelFullPath = outputDirectory + File.separator + testbenchModuleId + ".xml";
- SBMLDocument flattenDoc = flattenSBML(outputDirectory, hierModelFullPath);
- generateLPN(implementationModuleId, testbenchModuleId, flattenDoc);
- }
-
- public void generateLPN(String implementationModuleId, String testbenchModuleId, SBMLDocument sbmlDoc) {
+ SBMLDocument flattenDoc = flattenSBML(testbenchModuleId, outputDirectory);
WrappedSBML tbWrapper = getSBMLWrapper(testbenchModuleId);
WrappedSBML impWrapper = getSBMLWrapper(implementationModuleId);
- this.lpn = SBMLToLPN.convertSBMLtoLPN(tbWrapper, impWrapper, sbmlDoc);
+ this.lpn = SBMLToLPN.convertSBMLtoLPN(tbWrapper, impWrapper, flattenDoc);
}
/**
@@ -172,10 +185,16 @@ public class VerilogCompiler {
* This method will allow a user to access the SBMLWrapper based on the verilogModule_id that is assigned to the SBMLWrapper.
*
* @param verilogModule_id : The Verilog Module identifier is used to locate the SBMLWrapper the the verilog module was converted into.
- * @return The corresponding SBMLWrapper that is assigned to the given verilogModule_id
+ * @return The corresponding SBMLWrapper that is assigned to the given verilogModule_id.
+ * @throws FileNotFoundException
*/
- public WrappedSBML getSBMLWrapper(String verilogModule_id) {
- return this.vmoduleToSBML.get(verilogModule_id);
+ public WrappedSBML getSBMLWrapper(String verilogModule_id) throws FileNotFoundException {
+ WrappedSBML sbmlWrapper = this.vmoduleToSBML.get(verilogModule_id);
+ if(sbmlWrapper == null) {
+ throw new FileNotFoundException("Unable to locate the corresponding WrappedSBML object with the given verilogModule_id: " + verilogModule_id);
+
+ }
+ return sbmlWrapper;
}
public Map getMappedSBMLWrapper(){
@@ -193,7 +212,15 @@ public class VerilogCompiler {
public LPN getLPN(){
return this.lpn;
}
-
+
+ /**
+ * Export all SBML data compiled from verilog compiler. The output file names are assigned from the verilog module id.
+ * @param sbmlMapper: The compiled SBML data.
+ * @param outputDirectory: The directory where the SBML data will be exported to.
+ * @throws SBMLException
+ * @throws FileNotFoundException
+ * @throws XMLStreamException
+ */
public void exportSBML(Map sbmlMapper, String outputDirectory) throws SBMLException, FileNotFoundException, XMLStreamException{
for (Map.Entry entry : sbmlMapper.entrySet()) {
String verilogModuleId = entry.getKey();
@@ -201,11 +228,14 @@ public class VerilogCompiler {
exportSBML(sbmlDocument, outputDirectory + File.separator + verilogModuleId + ".xml");
}
}
-
- public void exportLPN(String outputDirectory, String outputFileName){
- exportLPN(this.lpn, outputDirectory + File.separator + outputFileName + ".lpn");
- }
-
+
+ /**
+ * Export all SBOL data compiled from verilog compiler. The output file names are assigned from the verilog module id.
+ * @param sbolMapper: The compiled SBOL data.
+ * @param outputDirectory: The directory where the SBOL data will be exported to.
+ * @throws IOException
+ * @throws SBOLConversionException
+ */
public void exportSBOL(Map sbolMapper, String outputDirectory) throws IOException, SBOLConversionException{
for (Map.Entry entry : sbolMapper.entrySet()) {
String verilogModuleId = entry.getKey();
@@ -214,7 +244,7 @@ public class VerilogCompiler {
}
}
- private void exportLPN(LPN lpn, String fullPath) {
+ public void exportLPN(LPN lpn, String fullPath) {
lpn.save(fullPath);
}
diff --git a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogConstructs/VerilogModuleInstance.java b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogConstructs/VerilogModuleInstance.java
index 94547928c..e76568d0e 100644
--- a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogConstructs/VerilogModuleInstance.java
+++ b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogConstructs/VerilogModuleInstance.java
@@ -36,11 +36,19 @@ public class VerilogModuleInstance implements AbstractVerilogConstruct {
public void setModuleReference(String moduleReference) {
this.moduleReference = moduleReference;
}
-
+
+ /**
+ * Get instantiated name of the submodule referenced.
+ * @return
+ */
public String getSubmoduleId() {
return this.submoduleId;
}
+ /**
+ * Get the referenced submodule id.
+ * @return
+ */
public String getModuleReference() {
return this.moduleReference;
}
diff --git a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogRunner.java b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogRunner.java
index 55ca8c90d..46688d08e 100644
--- a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogRunner.java
+++ b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogRunner.java
@@ -13,6 +13,7 @@ import org.apache.commons.cli.DefaultParser;
import org.apache.commons.cli.HelpFormatter;
import org.apache.commons.cli.Option;
import org.apache.commons.cli.Options;
+import org.sbml.jsbml.SBMLDocument;
import org.sbml.jsbml.text.parser.ParseException;
import org.sbolstandard.core2.SBOLConversionException;
import org.sbolstandard.core2.SBOLValidationException;
@@ -43,16 +44,21 @@ public class VerilogRunner {
if(compilerOptions.isGenerateSBOL()){
compiledVerilog.exportSBOL(compiledVerilog.getMappedSBOLWrapper(), outputDirectory);
}
- else{
- if(compilerOptions.isGenerateSBML()) {
- compiledVerilog.exportSBML(compiledVerilog.getMappedSBMLWrapper(), outputDirectory);
- }
- if(compilerOptions.isGenerateLPN()){
- compiledVerilog.generateLPN(compilerOptions.getImplementationModuleId(), compilerOptions.getTestbenchModuleId(), outputDirectory);
- compiledVerilog.exportLPN(outputDirectory, compilerOptions.getOutputFileName());
+
+ if(compilerOptions.isGenerateSBML()) {
+ compiledVerilog.exportSBML(compiledVerilog.getMappedSBMLWrapper(), outputDirectory);
+ if(compilerOptions.isOutputFlatModel()) {
+ SBMLDocument flattenDoc = compiledVerilog.flattenSBML(compilerOptions.getTestbenchModuleId(), compilerOptions.getOutputDirectory());
+ compiledVerilog.exportSBML(flattenDoc, outputDirectory + File.separator + compilerOptions.getOutputFileName() + ".xml");
}
}
+ if(compilerOptions.isGenerateLPN()){
+ compiledVerilog.generateLPN(compilerOptions.getImplementationModuleId(), compilerOptions.getTestbenchModuleId(), outputDirectory);
+ compiledVerilog.exportLPN(compiledVerilog.getLPN(), outputDirectory + File.separator + compilerOptions.getOutputFileName() + ".lpn");
+
+ }
+
}
catch (org.apache.commons.cli.ParseException e1) {
printUsage();
diff --git a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogToSBML.java b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogToSBML.java
index c9c9cbedb..bf4dccf9e 100644
--- a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogToSBML.java
+++ b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogToSBML.java
@@ -1,6 +1,5 @@
package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
-import java.util.HashMap;
import java.util.HashSet;
import java.util.LinkedList;
import java.util.List;
diff --git a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/WrappedSBML.java b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/WrappedSBML.java
index dabf4088a..039375c34 100644
--- a/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/WrappedSBML.java
+++ b/synthesis/src/main/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/WrappedSBML.java
@@ -3,7 +3,6 @@ package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
import java.util.ArrayList;
import java.util.HashMap;
import java.util.HashSet;
-import java.util.LinkedList;
import java.util.List;
import java.util.Map;
@@ -46,7 +45,6 @@ public class WrappedSBML {
private CompSBMLDocumentPlugin docPlugin;
private int placeCounter, transitionCounter, waitCounter, delayCounter;
private int condCounter, assignCounter;
- private LinkedList expressionQueue;
private List inputs;
private List outputs;
private Map submodulRef;
@@ -62,7 +60,6 @@ public class WrappedSBML {
this.model = sbmlDocument.createModel();
this.compPlugin = (CompModelPlugin) model.createPlugin(sbmlCompPack);
this.docPlugin = (CompSBMLDocumentPlugin) sbmlDocument.createPlugin(sbmlCompPack);
- this.expressionQueue = new LinkedList();
this.inputs = new ArrayList<>();
this.outputs = new ArrayList<>();
this.submodulRef = new HashMap();
@@ -89,10 +86,6 @@ public class WrappedSBML {
bool.setSBOTerm(602);
}
- public void addExpressionToQueue(String expression) {
- this.expressionQueue.addLast(expression);
- }
-
/**
*
* @param booleanId
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerOptions_Tests.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerOptions_Tests.java
index 2dc0839f2..f00f9f470 100644
--- a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerOptions_Tests.java
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerOptions_Tests.java
@@ -1,5 +1,6 @@
package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+import java.io.File;
import java.io.FileNotFoundException;
import java.io.IOException;
@@ -9,6 +10,7 @@ import org.apache.commons.cli.CommandLine;
import org.apache.commons.cli.ParseException;
import org.junit.Assert;
import org.junit.Test;
+import org.sbml.jsbml.SBMLDocument;
import org.sbolstandard.core2.SBOLConversionException;
import org.sbolstandard.core2.SBOLValidationException;
@@ -35,14 +37,22 @@ public class CompilerOptions_Tests{
if(setupOpt.isExportOn()) {
String outputDirectory = setupOpt.getOutputDirectory();
- if(setupOpt.isGenerateSBOL()) {
+ if(setupOpt.isGenerateSBOL()){
compiledVerilog.exportSBOL(compiledVerilog.getMappedSBOLWrapper(), outputDirectory);
}
- if(setupOpt.isGenerateSBML()){
- compiledVerilog.exportSBML(compiledVerilog.getMappedSBMLWrapper(), outputDirectory);
+
+ if(setupOpt.isGenerateSBML()) {
+ compiledVerilog.exportSBML(compiledVerilog.getMappedSBMLWrapper(), outputDirectory);
+ if(setupOpt.isOutputFlatModel()) {
+ SBMLDocument flattenDoc = compiledVerilog.flattenSBML(outputDirectory, outputDirectory);
+ compiledVerilog.exportSBML(flattenDoc, outputDirectory + setupOpt.getOutputFileName() + "_flattened.xml");
+ }
}
- if(setupOpt.isGenerateLPN()) {
- compiledVerilog.exportLPN(outputDirectory, setupOpt.getOutputFileName());
+
+ if(setupOpt.isGenerateLPN()){
+ compiledVerilog.generateLPN(setupOpt.getImplementationModuleId(), setupOpt.getTestbenchModuleId(), outputDirectory);
+ compiledVerilog.exportLPN(compiledVerilog.getLPN(), outputDirectory + File.separator + setupOpt.getOutputFileName());
+
}
}
return compiledVerilog;
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerTestSuite.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerTestSuite.java
index 45b784e0e..adcaf9f3b 100644
--- a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerTestSuite.java
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/CompilerTestSuite.java
@@ -16,7 +16,13 @@ import org.junit.runners.Suite.SuiteClasses;
CompilerOptions_Tests.class,
Decomposition_Test.class,
FlatteningSBML_Test.class,
- LPN_Example1_Test.class,
+ LPNExample1_Test.class,
+ LPNExample2_Test.class,
+ LPNExample3_Test.class,
+ LPNExample4_Test.class,
+ LPNExample5_Test.class,
+ LPNExample6_Test.class,
+ LPNExample7_Test.class,
VerilogParserExample1_Test.class,
VerilogParserExample2_Test.class,
VerilogParserExample3_Test.class,
@@ -36,6 +42,7 @@ import org.junit.runners.Suite.SuiteClasses;
VerilogParserEvenZeroes_Test.class,
VerilogParserMultThree_Test.class,
VerilogParserCounter_Test.class,
+ VerilogParserFilter_Test.class,
VerilogParserLFSR_Test.class,
VerilogParserSRLatch_Test.class,
VerilogParserScanflop_Test.class,
@@ -49,6 +56,7 @@ import org.junit.runners.Suite.SuiteClasses;
SBMLExample8_Test.class,
SBMLExample9_Test.class,
SBMLExample10_Test.class,
+ SBMLExample11_Test.class,
SBOLExample1_Test.class,
SBOLExample2_Test.class,
SBOLExample3_Test.class,
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPN_Example1_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample1_Test.java
similarity index 73%
rename from synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPN_Example1_Test.java
rename to synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample1_Test.java
index 2c0e37eb5..a27065e67 100644
--- a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPN_Example1_Test.java
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample1_Test.java
@@ -17,11 +17,11 @@ import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
import edu.utah.ece.async.lema.verification.lpn.LPN;
/**
- * Test verilog files containing implementation and testbench design compiled to one LPN model.
+ * Test lpn output for even zero design.
*
* @author Tramy Nguyen
*/
-public class LPN_Example1_Test {
+public class LPNExample1_Test {
private static LPN lpn;
@@ -49,12 +49,9 @@ public class LPN_Example1_Test {
Map expected_in = new HashMap();
expected_in.put("bit0", "false");
expected_in.put("bit1", "false");
-
- for (Map.Entry entry : lpn.getAllInputs().entrySet()) {
- String actual_key = entry.getKey();
- String actual_value = entry.getValue();
- Assert.assertEquals(expected_in.get(actual_key), actual_value);
- }
+
+ Assert.assertTrue(expected_in.keySet().equals(lpn.getAllInputs().keySet()));
+ Assert.assertTrue(expected_in.equals(lpn.getAllInputs()));
}
@Test
@@ -68,12 +65,9 @@ public class LPN_Example1_Test {
Map expected_out = new HashMap();
expected_out.put("parity0", "false");
expected_out.put("parity1", "false");
-
- for (Map.Entry entry : lpn.getAllOutputs().entrySet()) {
- String actual_key = entry.getKey();
- String actual_value = entry.getValue();
- Assert.assertEquals(expected_out.get(actual_key), actual_value);
- }
+
+ Assert.assertTrue(expected_out.keySet().equals(lpn.getAllOutputs().keySet()));
+ Assert.assertTrue(expected_out.equals(lpn.getAllOutputs()));
}
@Test
@@ -85,18 +79,14 @@ public class LPN_Example1_Test {
@Test
public void Test_booleans(){
Map expected_bool = new HashMap();
-
expected_bool.put("bit0", "false");
expected_bool.put("bit1", "false");
expected_bool.put("parity0", "false");
expected_bool.put("parity1", "false");
expected_bool.put("ez_instance__state", "false");
- for (Map.Entry entry : lpn.getBooleans().entrySet()) {
- String actual_key = entry.getKey();
- String actual_value = entry.getValue();
- Assert.assertEquals(expected_bool.get(actual_key), actual_value);
- }
+ Assert.assertTrue(expected_bool.keySet().equals(lpn.getBooleans().keySet()));
+ Assert.assertTrue(expected_bool.equals(lpn.getBooleans()));
}
@Test
@@ -104,14 +94,4 @@ public class LPN_Example1_Test {
Assert.assertEquals(52, lpn.getAllTransitions().length);
}
-
-
-
-
-
-
-
-
-
-
}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample2_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample2_Test.java
new file mode 100644
index 000000000..e1d7a0293
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample2_Test.java
@@ -0,0 +1,98 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+import java.util.HashMap;
+import java.util.Map;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.SBMLException;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+import edu.utah.ece.async.lema.verification.lpn.LPN;
+
+/**
+ * Test lpn output for counter design.
+ * @author Tramy Nguyen
+ */
+public class LPNExample2_Test {
+
+
+ private static LPN lpn;
+
+ @BeforeClass
+ public static void setupTest() throws XMLStreamException, IOException, BioSimException, VerilogCompilerException, SBMLException, ParseException, SBOLValidationException {
+
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogCounter_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogCounter_tbFile);
+
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ compiledVerilog.compileVerilogOutputData(true);
+ compiledVerilog.generateLPN("counter_imp", "counter_testbench", CompilerTestSuite.outputDirectory);
+
+ lpn = compiledVerilog.getLPN();
+ }
+
+ @Test
+ public void Test_inputSize(){
+ Assert.assertEquals(1, lpn.getAllInputs().size());
+ }
+
+ @Test
+ public void Test_inputs(){
+ Map expected_in = new HashMap();
+ expected_in.put("req", "false");
+
+ Assert.assertTrue(expected_in.keySet().equals(lpn.getAllInputs().keySet()));
+ Assert.assertTrue(expected_in.equals(lpn.getAllInputs()));
+ }
+
+ @Test
+ public void Test_outputSize(){
+ Assert.assertEquals(5, lpn.getAllOutputs().size());
+ }
+
+ @Test
+ public void Test_outputs(){
+ Map expected_out = new HashMap();
+ expected_out.put("a0", "false");
+ expected_out.put("a1", "false");
+ expected_out.put("b0", "false");
+ expected_out.put("b1", "false");
+ expected_out.put("ack", "false");
+
+ Assert.assertTrue(expected_out.keySet().equals(lpn.getAllOutputs().keySet()));
+ Assert.assertTrue(expected_out.equals(lpn.getAllOutputs()));
+ }
+
+ @Test
+ public void Test_booleanSize(){
+ Assert.assertEquals(8, lpn.getBooleans().size());
+
+ }
+
+ @Test
+ public void Test_booleans(){
+ Map expected_bool = new HashMap();
+ expected_bool.put("req", "false");
+ expected_bool.put("a0", "false");
+ expected_bool.put("a1", "false");
+ expected_bool.put("b0", "false");
+ expected_bool.put("b1", "false");
+ expected_bool.put("req", "false");
+ expected_bool.put("ack", "false");
+ expected_bool.put("req", "false");
+ expected_bool.put("counter_instance__state0", "false");
+ expected_bool.put("counter_instance__state1", "false");
+
+ Assert.assertTrue(expected_bool.keySet().equals(lpn.getBooleans().keySet()));
+ Assert.assertTrue(expected_bool.equals(lpn.getBooleans()));
+ }
+
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample3_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample3_Test.java
new file mode 100644
index 000000000..4bf656247
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample3_Test.java
@@ -0,0 +1,91 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+import java.util.HashMap;
+import java.util.Map;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.SBMLException;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+import edu.utah.ece.async.lema.verification.lpn.LPN;
+
+/**
+ * Test lpn output for filter design.
+ * @author Tramy Nguyen
+ *
+ */
+public class LPNExample3_Test {
+
+ private static LPN lpn;
+
+ @BeforeClass
+ public static void setupTest() throws XMLStreamException, IOException, BioSimException, VerilogCompilerException, SBMLException, ParseException, SBOLValidationException {
+
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogFilter_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogFilter_tbFile);
+
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ compiledVerilog.compileVerilogOutputData(true);
+ compiledVerilog.generateLPN("filter_imp", "filter_testbench", CompilerTestSuite.outputDirectory);
+
+ lpn = compiledVerilog.getLPN();
+ }
+
+ @Test
+ public void Test_inputSize(){
+ Assert.assertEquals(2, lpn.getAllInputs().size());
+ }
+
+ @Test
+ public void Test_inputs(){
+ Map expected_in = new HashMap();
+ expected_in.put("Start", "false");
+ expected_in.put("Sensor", "false");
+
+ Assert.assertTrue(expected_in.keySet().equals(lpn.getAllInputs().keySet()));
+ Assert.assertTrue(expected_in.equals(lpn.getAllInputs()));
+ }
+
+ @Test
+ public void Test_outputSize(){
+ Assert.assertEquals(3, lpn.getAllOutputs().size());
+ }
+
+ @Test
+ public void Test_outputs(){
+ Map expected_out = new HashMap();
+ expected_out.put("Actuator", "false");
+ expected_out.put("QS1", "false");
+ expected_out.put("QS2", "false");
+
+ Assert.assertTrue(expected_out.keySet().equals(lpn.getAllOutputs().keySet()));
+ Assert.assertTrue(expected_out.equals(lpn.getAllOutputs()));
+ }
+
+ @Test
+ public void Test_booleanSize(){
+ Assert.assertEquals(5, lpn.getBooleans().size());
+
+ }
+
+ @Test
+ public void Test_booleans(){
+ Map expected_bool = new HashMap();
+ expected_bool.put("Start", "false");
+ expected_bool.put("Sensor", "false");
+ expected_bool.put("QS1", "false");
+ expected_bool.put("QS2", "false");
+ expected_bool.put("Actuator", "false");
+
+ Assert.assertTrue(expected_bool.keySet().equals(lpn.getBooleans().keySet()));
+ Assert.assertTrue(expected_bool.equals(lpn.getBooleans()));
+ }
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample4_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample4_Test.java
new file mode 100644
index 000000000..663c3bc17
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample4_Test.java
@@ -0,0 +1,100 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+import java.util.HashMap;
+import java.util.Map;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.SBMLException;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+import edu.utah.ece.async.lema.verification.lpn.LPN;
+
+/**
+ * Test lpn output for lfsr design.
+ * @author Tramy Nguyen
+ *
+ */
+public class LPNExample4_Test {
+
+ private static LPN lpn;
+
+ @BeforeClass
+ public static void setupTest() throws XMLStreamException, IOException, BioSimException, VerilogCompilerException, SBMLException, ParseException, SBOLValidationException {
+
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogLFSR_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogLFSR_tbFile);
+
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ compiledVerilog.compileVerilogOutputData(true);
+ compiledVerilog.generateLPN("lfsr_imp", "lfsr_testbench", CompilerTestSuite.outputDirectory);
+
+ lpn = compiledVerilog.getLPN();
+ }
+
+ @Test
+ public void Test_inputSize(){
+ Assert.assertEquals(1, lpn.getAllInputs().size());
+ }
+
+ @Test
+ public void Test_inputs(){
+ Map expected_in = new HashMap();
+ expected_in.put("req", "false");
+
+ Assert.assertTrue(expected_in.keySet().equals(lpn.getAllInputs().keySet()));
+ Assert.assertTrue(expected_in.equals(lpn.getAllInputs()));
+ }
+
+ @Test
+ public void Test_outputSize(){
+ Assert.assertEquals(7, lpn.getAllOutputs().size());
+ }
+
+ @Test
+ public void Test_outputs(){
+ Map expected_out = new HashMap();
+ expected_out.put("ack", "false");
+ expected_out.put("a0", "false");
+ expected_out.put("a1", "false");
+ expected_out.put("b0", "false");
+ expected_out.put("b1", "false");
+ expected_out.put("c0", "false");
+ expected_out.put("c1", "false");
+
+ Assert.assertTrue(expected_out.keySet().equals(lpn.getAllOutputs().keySet()));
+ Assert.assertTrue(expected_out.equals(lpn.getAllOutputs()));
+ }
+
+ @Test
+ public void Test_booleanSize(){
+ Assert.assertEquals(11, lpn.getBooleans().size());
+
+ }
+
+ @Test
+ public void Test_booleans(){
+ Map expected_bool = new HashMap();
+ expected_bool.put("req", "false");
+ expected_bool.put("ack", "false");
+ expected_bool.put("a0", "false");
+ expected_bool.put("a1", "false");
+ expected_bool.put("b0", "false");
+ expected_bool.put("b1", "false");
+ expected_bool.put("c0", "false");
+ expected_bool.put("c1", "false");
+ expected_bool.put("lfsr_instance__feedback", "false");
+ expected_bool.put("lfsr_instance__state0", "false");
+ expected_bool.put("lfsr_instance__state1", "false");
+
+ Assert.assertTrue(expected_bool.keySet().equals(lpn.getBooleans().keySet()));
+ Assert.assertTrue(expected_bool.equals(lpn.getBooleans()));
+ }
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample5_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample5_Test.java
new file mode 100644
index 000000000..9db086fcc
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample5_Test.java
@@ -0,0 +1,92 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+import java.util.HashMap;
+import java.util.Map;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.SBMLException;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+import edu.utah.ece.async.lema.verification.lpn.LPN;
+
+/**
+ * Test lpn output for multiple of three design.
+ * @author Tramy Nguyen
+ *
+ */
+public class LPNExample5_Test {
+
+ private static LPN lpn;
+
+ @BeforeClass
+ public static void setupTest() throws XMLStreamException, IOException, BioSimException, VerilogCompilerException, SBMLException, ParseException, SBOLValidationException {
+
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogMultThree_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogMultThree_tbFile);
+
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ compiledVerilog.compileVerilogOutputData(true);
+ compiledVerilog.generateLPN("multthree_imp", "multThree_testbench", CompilerTestSuite.outputDirectory);
+
+ lpn = compiledVerilog.getLPN();
+ }
+
+ @Test
+ public void Test_inputSize(){
+ Assert.assertEquals(2, lpn.getAllInputs().size());
+ }
+
+ @Test
+ public void Test_inputs(){
+ Map expected_in = new HashMap();
+ expected_in.put("bit0", "false");
+ expected_in.put("bit1", "false");
+
+ Assert.assertTrue(expected_in.keySet().equals(lpn.getAllInputs().keySet()));
+ Assert.assertTrue(expected_in.equals(lpn.getAllInputs()));
+ }
+
+ @Test
+ public void Test_outputSize(){
+ Assert.assertEquals(2, lpn.getAllOutputs().size());
+ }
+
+ @Test
+ public void Test_outputs(){
+ Map expected_out = new HashMap();
+ expected_out.put("parity0", "false");
+ expected_out.put("parity1", "false");
+
+ Assert.assertTrue(expected_out.keySet().equals(lpn.getAllOutputs().keySet()));
+ Assert.assertTrue(expected_out.equals(lpn.getAllOutputs()));
+ }
+
+ @Test
+ public void Test_booleanSize(){
+ Assert.assertEquals(7, lpn.getBooleans().size());
+
+ }
+
+ @Test
+ public void Test_booleans(){
+ Map expected_bool = new HashMap();
+ expected_bool.put("bit0", "false");
+ expected_bool.put("bit1", "false");
+ expected_bool.put("parity0", "false");
+ expected_bool.put("parity1", "false");
+ expected_bool.put("mt_instance__state0", "false");
+ expected_bool.put("mt_instance__state1", "false");
+ expected_bool.put("mt_instance__temp", "false");
+
+ Assert.assertTrue(expected_bool.keySet().equals(lpn.getBooleans().keySet()));
+ Assert.assertTrue(expected_bool.equals(lpn.getBooleans()));
+ }
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample6_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample6_Test.java
new file mode 100644
index 000000000..32b3b37e4
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample6_Test.java
@@ -0,0 +1,102 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+import java.util.HashMap;
+import java.util.Map;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.SBMLException;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+import edu.utah.ece.async.lema.verification.lpn.LPN;
+
+/**
+ * Test lpn output for scanflop design
+ * @author Tramy Nguyen
+ *
+ */
+public class LPNExample6_Test {
+
+ private static LPN lpn;
+
+ @BeforeClass
+ public static void setupTest() throws XMLStreamException, IOException, BioSimException, VerilogCompilerException, SBMLException, ParseException, SBOLValidationException {
+
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogScanflop_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogScanflop_tbFile);
+
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ compiledVerilog.compileVerilogOutputData(true);
+ compiledVerilog.generateLPN("scanflop_imp", "scanflop_testbench", CompilerTestSuite.outputDirectory);
+
+ lpn = compiledVerilog.getLPN();
+ }
+
+ @Test
+ public void Test_inputSize(){
+ Assert.assertEquals(7, lpn.getAllInputs().size());
+ }
+
+ @Test
+ public void Test_inputs(){
+ Map expected_in = new HashMap();
+ expected_in.put("in1_0", "false");
+ expected_in.put("in1_1", "false");
+ expected_in.put("in2_0", "false");
+ expected_in.put("in2_1", "false");
+ expected_in.put("sel0", "false");
+ expected_in.put("sel1", "false");
+ expected_in.put("req", "false");
+
+ Assert.assertTrue(expected_in.keySet().equals(lpn.getAllInputs().keySet()));
+ Assert.assertTrue(expected_in.equals(lpn.getAllInputs()));
+ }
+
+ @Test
+ public void Test_outputSize(){
+ Assert.assertEquals(3, lpn.getAllOutputs().size());
+ }
+
+ @Test
+ public void Test_outputs(){
+ Map expected_out = new HashMap();
+ expected_out.put("q1", "false");
+ expected_out.put("q0", "false");
+ expected_out.put("ack", "false");
+
+ Assert.assertTrue(expected_out.keySet().equals(lpn.getAllOutputs().keySet()));
+ Assert.assertTrue(expected_out.equals(lpn.getAllOutputs()));
+ }
+
+ @Test
+ public void Test_booleanSize(){
+ Assert.assertEquals(11, lpn.getBooleans().size());
+
+ }
+
+ @Test
+ public void Test_booleans(){
+ Map expected_bool = new HashMap();
+ expected_bool.put("in1_0", "false");
+ expected_bool.put("in1_1", "false");
+ expected_bool.put("in2_0", "false");
+ expected_bool.put("in2_1", "false");
+ expected_bool.put("sel0", "false");
+ expected_bool.put("sel1", "false");
+ expected_bool.put("req", "false");
+ expected_bool.put("q1", "false");
+ expected_bool.put("q0", "false");
+ expected_bool.put("ack", "false");
+ expected_bool.put("sf_instance__state", "false");
+
+ Assert.assertTrue(expected_bool.keySet().equals(lpn.getBooleans().keySet()));
+ Assert.assertTrue(expected_bool.equals(lpn.getBooleans()));
+ }
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample7_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample7_Test.java
new file mode 100644
index 000000000..f003f179e
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/LPNExample7_Test.java
@@ -0,0 +1,89 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+import java.util.HashMap;
+import java.util.Map;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.SBMLException;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+import edu.utah.ece.async.lema.verification.lpn.LPN;
+
+/**
+ * Test lpn output for srlatch design
+ * @author Tramy Nguyen
+ *
+ */
+public class LPNExample7_Test {
+
+ private static LPN lpn;
+
+ @BeforeClass
+ public static void setupTest() throws XMLStreamException, IOException, BioSimException, VerilogCompilerException, SBMLException, ParseException, SBOLValidationException {
+
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogSRLatch_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogSRLatch_tbFile);
+
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ compiledVerilog.compileVerilogOutputData(true);
+ compiledVerilog.generateLPN("srlatch_imp", "srlatch_testbench", CompilerTestSuite.outputDirectory);
+
+ lpn = compiledVerilog.getLPN();
+ }
+
+ @Test
+ public void Test_inputSize(){
+ Assert.assertEquals(2, lpn.getAllInputs().size());
+ }
+
+ @Test
+ public void Test_inputs(){
+ Map expected_in = new HashMap();
+ expected_in.put("s", "false");
+ expected_in.put("r", "false");
+
+ Assert.assertTrue(expected_in.keySet().equals(lpn.getAllInputs().keySet()));
+ Assert.assertTrue(expected_in.equals(lpn.getAllInputs()));
+ }
+
+ @Test
+ public void Test_outputSize(){
+ Assert.assertEquals(2, lpn.getAllOutputs().size());
+ }
+
+ @Test
+ public void Test_outputs(){
+ Map expected_out = new HashMap();
+ expected_out.put("q", "false");
+ expected_out.put("ack", "false");
+
+ Assert.assertTrue(expected_out.keySet().equals(lpn.getAllOutputs().keySet()));
+ Assert.assertTrue(expected_out.equals(lpn.getAllOutputs()));
+ }
+
+ @Test
+ public void Test_booleanSize(){
+ Assert.assertEquals(4, lpn.getBooleans().size());
+
+ }
+
+ @Test
+ public void Test_booleans(){
+ Map expected_bool = new HashMap();
+ expected_bool.put("s", "false");
+ expected_bool.put("r", "false");
+ expected_bool.put("q", "false");
+ expected_bool.put("ack", "false");
+
+ Assert.assertTrue(expected_bool.keySet().equals(lpn.getBooleans().keySet()));
+ Assert.assertTrue(expected_bool.equals(lpn.getBooleans()));
+ }
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBMLExample11_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBMLExample11_Test.java
new file mode 100644
index 000000000..b6639a5f3
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBMLExample11_Test.java
@@ -0,0 +1,237 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.InitialAssignment;
+import org.sbml.jsbml.Model;
+import org.sbml.jsbml.Parameter;
+import org.sbml.jsbml.ext.comp.CompModelPlugin;
+import org.sbml.jsbml.ext.comp.CompSBasePlugin;
+import org.sbml.jsbml.ext.comp.Port;
+import org.sbml.jsbml.ext.comp.ReplacedBy;
+import org.sbml.jsbml.ext.comp.ReplacedElement;
+import org.sbml.jsbml.ext.comp.Submodel;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLConversionException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+
+/**
+ * Test replacement and replacedBy objects for SBML conversion
+ * @author Tramy Nguyen
+ *
+ */
+public class SBMLExample11_Test {
+
+ private static Model tbModel, impModel;
+
+ @BeforeClass
+ public static void setupTest() throws ParseException, SBOLValidationException, VerilogCompilerException, XMLStreamException, IOException, BioSimException, org.apache.commons.cli.ParseException, SBOLConversionException {
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogFilter_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogFilter_tbFile);
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ compiledVerilog.compileVerilogOutputData(setupOpt.isOutputFlatModel());
+
+ WrappedSBML tbWrapper = compiledVerilog.getSBMLWrapper("filter_testbench");
+ Assert.assertNotNull(tbWrapper);
+ tbModel = tbWrapper.getModel();
+ Assert.assertNotNull(tbModel);
+ Assert.assertEquals("filter_testbench", tbModel.getId());
+
+ WrappedSBML impWrapper = compiledVerilog.getSBMLWrapper("filter_imp");
+ Assert.assertNotNull(impWrapper);
+ impModel = impWrapper.getModel();
+ Assert.assertNotNull(impModel);
+ Assert.assertEquals("filter_imp", impModel.getId());
+ }
+
+ @Test
+ public void TestSBML_tbPorts() {
+ CompModelPlugin compPlugin = (CompModelPlugin) tbModel.getPlugin("comp");
+ Assert.assertEquals(0, compPlugin.getNumPorts());
+ }
+
+ @Test
+ public void TestSBML_impPortSize() {
+ CompModelPlugin compPlugin = (CompModelPlugin) impModel.getPlugin("comp");
+ Assert.assertEquals(3, compPlugin.getNumPorts());
+ }
+
+ @Test
+ public void TestSBML_impPorts() {
+ CompModelPlugin compPort = (CompModelPlugin) impModel.getPlugin("comp");
+ for(Port port : compPort.getListOfPorts()){
+ if(port.getId().equals("filter_imp__Start")) {
+ Assert.assertEquals("Start", port.getIdRef());
+ }
+ else if(port.getId().equals("filter_imp__Sensor")) {
+ Assert.assertEquals("Sensor", port.getIdRef());
+ }
+ else if(port.getId().equals("filter_imp__Actuator")) {
+ Assert.assertEquals("Actuator", port.getIdRef());
+ }
+ else {
+ Assert.fail("Unexpected port found with the following id: " + port.getId());
+ }
+ }
+ }
+
+ @Test
+ public void TestSBML_tbSubmoduleSize() {
+ CompModelPlugin compPlugin = (CompModelPlugin) tbModel.getPlugin("comp");
+ Assert.assertEquals(3, compPlugin.getNumSubmodels());
+ }
+
+ @Test
+ public void TestSBML_tbSubmodule() {
+ CompModelPlugin modelPlugin = (CompModelPlugin) tbModel.getPlugin("comp");
+ for(Submodel model : modelPlugin.getListOfSubmodels()){
+ Assert.assertTrue(model.getId().equals("cell1") || model.getId().equals("cell2") || model.getId().equals("cell3"));
+ Assert.assertEquals("filter_imp", model.getModelRef());
+ }
+ }
+
+ @Test
+ public void TestSBML_impParameterSize() {
+ Assert.assertEquals(10, impModel.getNumParameters());
+ }
+
+ @Test
+ public void TestSBML_tbParameterSize() {
+ Assert.assertEquals(36, tbModel.getNumParameters());
+ }
+
+ @Test
+ public void Test_tbSensorReplacement() {
+ Parameter sensor = tbModel.getParameter("Sensor");
+ Assert.assertNotNull(sensor);
+
+ Assert.assertTrue(sensor.isSetPlugin("comp"));
+ CompSBasePlugin sbasePlugin = (CompSBasePlugin)sensor.getPlugin("comp");
+
+ Assert.assertEquals(3, sbasePlugin.getNumReplacedElements());
+ for(ReplacedElement sensorReplacement : sbasePlugin.getListOfReplacedElements()) {
+ Assert.assertEquals("filter_imp__Sensor", sensorReplacement.getPortRef());
+ boolean expectedRef = sensorReplacement.getSubmodelRef().equals("cell1") || sensorReplacement.getSubmodelRef().equals("cell2") || sensorReplacement.getSubmodelRef().equals("cell3");
+ Assert.assertTrue(expectedRef);
+ }
+ }
+
+ @Test
+ public void Test_tbStartReplacement() {
+ Parameter sensor = tbModel.getParameter("Start");
+ Assert.assertNotNull(sensor);
+
+ Assert.assertTrue(sensor.isSetPlugin("comp"));
+ CompSBasePlugin sbasePlugin = (CompSBasePlugin)sensor.getPlugin("comp");
+
+ Assert.assertEquals(1, sbasePlugin.getNumReplacedElements());
+ ReplacedElement startReplacement = sbasePlugin.getReplacedElement(0);
+ Assert.assertNotNull(startReplacement);
+ Assert.assertEquals("filter_imp__Start", startReplacement.getPortRef());
+ Assert.assertEquals("cell1", startReplacement.getSubmodelRef());
+ }
+
+ @Test
+ public void Test_tbActuatorReplacedBy() {
+ Parameter actuator = tbModel.getParameter("Actuator");
+ Assert.assertNotNull(actuator);
+
+ Assert.assertTrue(actuator.isSetPlugin("comp"));
+ CompSBasePlugin sbasePlugin = (CompSBasePlugin) actuator.getPlugin("comp");
+
+ ReplacedBy actuatorReplacedBy = sbasePlugin.getReplacedBy();
+ Assert.assertEquals("filter_imp__Actuator", actuatorReplacedBy.getPortRef());
+ Assert.assertTrue(actuatorReplacedBy.getSubmodelRef().equals("cell3"));
+ }
+
+ @Test
+ public void Test_tbQS1ReplacedBy() {
+ Parameter QS1 = tbModel.getParameter("QS1");
+ Assert.assertNotNull(QS1);
+
+ Assert.assertTrue(QS1.isSetPlugin("comp"));
+ CompSBasePlugin sbasePlugin = (CompSBasePlugin) QS1.getPlugin("comp");
+
+ ReplacedBy actuatorReplacedBy = sbasePlugin.getReplacedBy();
+ Assert.assertEquals("filter_imp__Actuator", actuatorReplacedBy.getPortRef());
+ Assert.assertTrue(actuatorReplacedBy.getSubmodelRef().equals("cell1"));
+ }
+
+ @Test
+ public void Test_tbQS2ReplacedBy() {
+ Parameter QS2 = tbModel.getParameter("QS2");
+ Assert.assertNotNull(QS2);
+
+ Assert.assertTrue(QS2.isSetPlugin("comp"));
+ CompSBasePlugin sbasePlugin = (CompSBasePlugin) QS2.getPlugin("comp");
+
+ ReplacedBy actuatorReplacedBy = sbasePlugin.getReplacedBy();
+ Assert.assertEquals("filter_imp__Actuator", actuatorReplacedBy.getPortRef());
+ Assert.assertTrue(actuatorReplacedBy.getSubmodelRef().equals("cell2"));
+ }
+
+ @Test
+ public void Test_tbQS1Replacement() {
+ Parameter qs1 = tbModel.getParameter("QS1");
+ Assert.assertNotNull(qs1);
+
+ Assert.assertTrue(qs1.isSetPlugin("comp"));
+ CompSBasePlugin sbasePlugin = (CompSBasePlugin)qs1.getPlugin("comp");
+
+ Assert.assertEquals(1, sbasePlugin.getNumReplacedElements());
+ ReplacedElement startReplacement = sbasePlugin.getReplacedElement(0);
+ Assert.assertNotNull(startReplacement);
+ Assert.assertEquals("filter_imp__Start", startReplacement.getPortRef());
+ Assert.assertEquals("cell2", startReplacement.getSubmodelRef());
+ }
+
+ @Test
+ public void Test_tbQS2Replacement() {
+ Parameter qs2 = tbModel.getParameter("QS2");
+ Assert.assertNotNull(qs2);
+
+ Assert.assertTrue(qs2.isSetPlugin("comp"));
+ CompSBasePlugin sbasePlugin = (CompSBasePlugin)qs2.getPlugin("comp");
+
+ Assert.assertEquals(1, sbasePlugin.getNumReplacedElements());
+ ReplacedElement startReplacement = sbasePlugin.getReplacedElement(0);
+ Assert.assertNotNull(startReplacement);
+ Assert.assertEquals("filter_imp__Start", startReplacement.getPortRef());
+ Assert.assertEquals("cell3", startReplacement.getSubmodelRef());
+ }
+
+ @Test
+ public void TestSBML_impInitialAssignmentSize() {
+ Assert.assertEquals(1, impModel.getNumInitialAssignments());
+ }
+
+ @Test
+ public void TestSBML_tbInitialAssignmentSize() {
+ Assert.assertEquals(2, tbModel.getNumInitialAssignments());
+ }
+
+ @Test
+ public void TestSBML_impInitialAssignment() {
+ InitialAssignment assign = impModel.getInitialAssignment(0);
+ Assert.assertEquals("Actuator", assign.getVariable());
+ Assert.assertTrue(assign.getMath().isInteger());
+ Assert.assertEquals(0, assign.getMath().getInteger());
+ }
+
+ @Test
+ public void TestSBML_tbInitialAssignment() {
+ for(InitialAssignment assign : tbModel.getListOfInitialAssignments()){
+ Assert.assertTrue(assign.getVariable().equals("Start") || assign.getVariable().equals("Sensor"));
+ Assert.assertTrue(assign.getMath().isInteger());
+ Assert.assertEquals(0, assign.getMath().getInteger());
+ }
+ }
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBOLExample2_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBOLExample2_Test.java
index b5028655d..7766bc4ca 100644
--- a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBOLExample2_Test.java
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/SBOLExample2_Test.java
@@ -1,6 +1,5 @@
package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
-import static org.junit.Assert.fail;
import java.io.IOException;
import java.net.URI;
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogParserFilter_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogParserFilter_Test.java
new file mode 100644
index 000000000..86dba823b
--- /dev/null
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/VerilogParserFilter_Test.java
@@ -0,0 +1,93 @@
+package edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler;
+
+import java.io.IOException;
+import java.util.HashMap;
+import java.util.Map;
+
+import javax.xml.stream.XMLStreamException;
+
+import org.junit.Assert;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import org.sbml.jsbml.text.parser.ParseException;
+import org.sbolstandard.core2.SBOLConversionException;
+import org.sbolstandard.core2.SBOLValidationException;
+
+import edu.utah.ece.async.ibiosim.dataModels.util.exceptions.BioSimException;
+import edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler.VerilogConstructs.VerilogModule;
+import edu.utah.ece.async.ibiosim.synthesis.VerilogCompiler.VerilogConstructs.VerilogModuleInstance;
+
+/**
+ * Test multiple submodules referencing the same verilog design specification.
+ * @author Tramy Nguyen
+ *
+ */
+public class VerilogParserFilter_Test {
+ private static VerilogModule verilog_tb;
+
+ @BeforeClass
+ public static void setupTest() throws ParseException, SBOLValidationException, VerilogCompilerException, XMLStreamException, IOException, BioSimException, org.apache.commons.cli.ParseException, SBOLConversionException {
+ CompilerOptions setupOpt = new CompilerOptions();
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogFilter_impFile);
+ setupOpt.addVerilogFile(CompilerTestSuite.verilogFilter_tbFile);
+
+ VerilogCompiler compiledVerilog = VerilogRunner.compile(setupOpt.getVerilogFiles());
+ Map moduleList = compiledVerilog.getVerilogModules();
+ Assert.assertEquals(2, moduleList.size());
+
+ verilog_tb = moduleList.get("filter_testbench");
+ Assert.assertNotNull(verilog_tb);
+ }
+
+ @Test
+ public void Test_tbSubmodelSize() {
+ Assert.assertEquals(3, verilog_tb.getNumSubmodules());
+ }
+
+ @Test
+ public void Test_tbSubmodelNames() {
+ for(VerilogModuleInstance module : verilog_tb.getSubmodules()){
+ Assert.assertTrue(module.getSubmoduleId().equals("cell1") || module.getSubmoduleId().equals("cell2") || module.getSubmoduleId().equals("cell3"));
+ Assert.assertEquals("filter_imp", module.getModuleReference());
+ }
+ }
+
+ @Test
+ public void Test_tb_subMod1Connections() {
+ VerilogModuleInstance submodule = verilog_tb.getSubmodule(0);
+
+ Map expectedConnections = new HashMap<>();
+ expectedConnections.put("Start", "Start");
+ expectedConnections.put("Sensor", "Sensor");
+ expectedConnections.put("QS1", "Actuator");
+
+ Assert.assertTrue(expectedConnections.keySet().equals(submodule.getNamedConnections().keySet()));
+ Assert.assertTrue(expectedConnections.equals(submodule.getNamedConnections()));
+ }
+
+ @Test
+ public void Test_tb_subMod2Connections() {
+ VerilogModuleInstance submodule = verilog_tb.getSubmodule(1);
+
+ Map expectedConnections = new HashMap<>();
+ expectedConnections.put("QS1", "Start");
+ expectedConnections.put("Sensor", "Sensor");
+ expectedConnections.put("QS2", "Actuator");
+
+ Assert.assertTrue(expectedConnections.keySet().equals(submodule.getNamedConnections().keySet()));
+ Assert.assertTrue(expectedConnections.equals(submodule.getNamedConnections()));
+ }
+
+ @Test
+ public void Test_tb_subMod3Connections() {
+ VerilogModuleInstance submodule = verilog_tb.getSubmodule(2);
+
+ Map expectedConnections = new HashMap<>();
+ expectedConnections.put("QS2", "Start");
+ expectedConnections.put("Sensor", "Sensor");
+ expectedConnections.put("Actuator", "Actuator");
+
+ Assert.assertTrue(expectedConnections.keySet().equals(submodule.getNamedConnections().keySet()));
+ Assert.assertTrue(expectedConnections.equals(submodule.getNamedConnections()));
+ }
+}
diff --git a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/Workflow_Test.java b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/Workflow_Test.java
index 5348d74d6..55cd2a54e 100644
--- a/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/Workflow_Test.java
+++ b/synthesis/src/test/java/edu/utah/ece/async/ibiosim/synthesis/VerilogCompiler/Workflow_Test.java
@@ -29,7 +29,7 @@ public class Workflow_Test {
String files = String.join(" ", CompilerTestSuite.verilogEvenZero_impFile, CompilerTestSuite.verilogEvenZero_tbFile);
String[] cmd = {"-v", files,
"-imp", "evenzeroes_imp", "-tb", "evenzeroes_testbench",
- "-sbml", "-flat", "-od", CompilerTestSuite.outputDirectory};
+ "-sbml", "-flat", "-od", CompilerTestSuite.outputDirectory, "-o", "evenzeroes_imp_evenzeroes_testbench_flattened"};
VerilogRunner.main(cmd);
}
diff --git a/synthesis/src/test/resources/init_block.v b/synthesis/src/test/resources/init_block.v
index 931f1e60c..e4bda1442 100644
--- a/synthesis/src/test/resources/init_block.v
+++ b/synthesis/src/test/resources/init_block.v
@@ -5,14 +5,15 @@
// ----------------------------
module init_block(in0, out0);
-
+
input in0;
output reg out0;
- reg state;
-
+ reg state;
+
initial begin
out0 = 1'b0;
state = 1'b1;
end
-endmodule
\ No newline at end of file
+
+endmodule
diff --git a/synthesis/src/test/resources/outputFiles/Start_Sensor_Actuator_net.xml b/synthesis/src/test/resources/outputFiles/Start_Sensor_Actuator_net.xml
index 866ddfe1e..b3f760826 100644
--- a/synthesis/src/test/resources/outputFiles/Start_Sensor_Actuator_net.xml
+++ b/synthesis/src/test/resources/outputFiles/Start_Sensor_Actuator_net.xml
@@ -4,6 +4,56 @@
circuit_Start_Sensor_Actuator_net
1.0
+
+
+
+ FC8_norTU
+ 1.0
+
+
+
+
+
+
+
+
+ FC13_norTU
+ 1.0
+
+
+
+
+
+
+
+
+ FC1_Sensor
+ 1.0
+
+
+
+
+
+
+
+
+ FC14_wiredProtein
+ 1.0
+
+
+
+
+
+
+
+
+ FC12_notTU
+ 1.0
+
+
+
+
+
@@ -14,6 +64,36 @@
+
+
+
+ FC10_wiredProtein
+ 1.0
+
+
+
+
+
+
+
+
+ FC4_wiredProtein
+ 1.0
+
+
+
+
+
+
+
+
+ FC15_notTU
+ 1.0
+
+
+
+
+
@@ -24,16 +104,6 @@
-
-
-
- FC9_wiredProtein
- 1.0
-
-
-
-
-
@@ -45,11 +115,21 @@
-
-
- FC14_wiredProtein
+
+
+ FC5_norTU
1.0
-
+
+
+
+
+
+
+
+
+ FC9_wiredProtein
+ 1.0
+
@@ -74,76 +154,6 @@
-
-
-
- FC13_norTU
- 1.0
-
-
-
-
-
-
-
-
- FC12_notTU
- 1.0
-
-
-
-
-
-
-
-
- FC1_Sensor
- 1.0
-
-
-
-
-
-
-
-
- FC5_norTU
- 1.0
-
-
-
-
-
-
-
-
- FC10_wiredProtein
- 1.0
-
-
-
-
-
-
-
-
- FC8_norTU
- 1.0
-
-
-
-
-
-
-
-
- FC15_notTU
- 1.0
-
-
-
-
-
@@ -154,16 +164,6 @@
-
-
-
- FC4_wiredProtein
- 1.0
-
-
-
-
-
@@ -627,6 +627,49 @@
+
+
+ CD31_notTU
+ 1.0
+
+
+
+
+
+ C21_part
+ 1.0
+
+
+
+
+
+
+
+ C19_part
+ 1.0
+
+
+
+
+
+
+
+ C20_part
+ 1.0
+
+
+
+
+
+
+
+ C18_part
+ 1.0
+
+
+
+
+
CD14_terminator
@@ -695,6 +738,374 @@
+
+
+ CD19_norTU
+ 1.0
+
+
+
+
+
+ C12_part
+ 1.0
+
+
+
+
+
+
+
+ C9_part
+ 1.0
+
+
+
+
+
+
+
+ C13_part
+ 1.0
+
+
+
+
+
+
+
+ C11_part
+ 1.0
+
+
+
+
+
+
+
+ C10_part
+ 1.0
+
+
+
+
+
+
+
+ CD21_cds
+ 1.0
+
+
+
+
+
+ CD10_promoter
+ 1.0
+
+
+
+
+
+ CD42_promoter
+ 1.0
+
+
+
+
+
+ CD26_notTU
+ 1.0
+
+
+
+
+
+ C17_part
+ 1.0
+
+
+
+
+
+
+
+ C14_part
+ 1.0
+
+
+
+
+
+
+
+ C16_part
+ 1.0
+
+
+
+
+
+
+
+ C15_part
+ 1.0
+
+
+
+
+
+
+
+ CD0_Start
+ 1.0
+
+
+
+
+ CD35_promoter
+ 1.0
+
+
+
+
+
+ CD11_norTU
+ 1.0
+
+
+
+
+
+ C8_part
+ 1.0
+
+
+
+
+
+
+
+ C4_part
+ 1.0
+
+
+
+
+
+
+
+ C5_part
+ 1.0
+
+
+
+
+
+
+
+ C7_part
+ 1.0
+
+
+
+
+
+
+
+ C6_part
+ 1.0
+
+
+
+
+
+
+
+ CD43_notTU
+ 1.0
+
+
+
+
+
+ C28_part
+ 1.0
+
+
+
+
+
+
+
+ C30_part
+ 1.0
+
+
+
+
+
+
+
+ C27_part
+ 1.0
+
+
+
+
+
+
+
+ C29_part
+ 1.0
+
+
+
+
+
+
+
+ CD17_promoter
+ 1.0
+
+
+
+
+
+ CD4_notTU
+ 1.0
+
+
+
+
+
+ C1_part
+ 1.0
+
+
+
+
+
+
+
+ C0_part
+ 1.0
+
+
+
+
+
+
+
+ C3_part
+ 1.0
+
+
+
+
+
+
+
+ C2_part
+ 1.0
+
+
+
+
+
+
+
+ CD45_cds
+ 1.0
+
+
+
+
+
+ CD44_ribosome
+ 1.0
+
+
+
+
+
+ CD16_wiredProtein
+ 1.0
+
+
+
+
+ CD38_ribosome
+ 1.0
+
+
+
+
+
+ CD7_terminator
+ 1.0
+
+
+
+
+
+ CD2_Actuator
+ 1.0
+
+
+
+
+ CD33_cds
+ 1.0
+
+
+
+
+
+ CD12_ribosome
+ 1.0
+
+
+
+
+
+ CD34_terminator
+ 1.0
+
+
+
+
+
+ CD41_wiredProtein
+ 1.0
+
+
+
+
+ CD39_cds
+ 1.0
+
+
+
+
+
+ CD30_promoter
+ 1.0
+
+
+
+
+
+ CD40_terminator
+ 1.0
+
+
+
+
+
+ CD23_wiredProtein
+ 1.0
+
+
CD37_norTU
@@ -747,365 +1158,6 @@
-
-
- CD21_cds
- 1.0
-
-
-
-
-
- CD10_promoter
- 1.0
-
-
-
-
-
- CD42_promoter
- 1.0
-
-
-
-
-
- CD0_Start
- 1.0
-
-
-
-
- CD43_notTU
- 1.0
-
-
-
-
-
- C30_part
- 1.0
-
-
-
-
-
-
-
- C27_part
- 1.0
-
-
-
-
-
-
-
- C28_part
- 1.0
-
-
-
-
-
-
-
- C29_part
- 1.0
-
-
-
-
-
-
-
- CD4_notTU
- 1.0
-
-
-
-
-
- C1_part
- 1.0
-
-
-
-
-
-
-
- C0_part
- 1.0
-
-
-
-
-
-
-
- C3_part
- 1.0
-
-
-
-
-
-
-
- C2_part
- 1.0
-
-
-
-
-
-
-
- CD35_promoter
- 1.0
-
-
-
-
-
- CD17_promoter
- 1.0
-
-
-
-
-
- CD26_notTU
- 1.0
-
-
-
-
-
- C17_part
- 1.0
-
-
-
-
-
-
-
- C14_part
- 1.0
-
-
-
-
-
-
-
- C16_part
- 1.0
-
-
-
-
-
-
-
- C15_part
- 1.0
-
-
-
-
-
-
-
- CD45_cds
- 1.0
-
-
-
-
-
- CD44_ribosome
- 1.0
-
-
-
-
-
- CD16_wiredProtein
- 1.0
-
-
-
-
- CD38_ribosome
- 1.0
-
-
-
-
-
- CD7_terminator
- 1.0
-
-
-
-
-
- CD2_Actuator
- 1.0
-
-
-
-
- CD33_cds
- 1.0
-
-
-
-
-
- CD31_notTU
- 1.0
-
-
-
-
-
- C18_part
- 1.0
-
-
-
-
-
-
-
- C19_part
- 1.0
-
-
-
-
-
-
-
- C21_part
- 1.0
-
-
-
-
-
-
-
- C20_part
- 1.0
-
-
-
-
-
-
-
- CD12_ribosome
- 1.0
-
-
-
-
-
- CD34_terminator
- 1.0
-
-
-
-
-
- CD41_wiredProtein
- 1.0
-
-
-
-
- CD39_cds
- 1.0
-
-
-
-
-
- CD11_norTU
- 1.0
-
-
-
-
-
- C8_part
- 1.0
-
-
-
-
-
-
-
- C7_part
- 1.0
-
-
-
-
-
-
-
- C6_part
- 1.0
-
-
-
-
-
-
-
- C5_part
- 1.0
-
-
-
-
-
-
-
- C4_part
- 1.0
-
-
-
-
-
-
-
- CD30_promoter
- 1.0
-
-
-
-
-
- CD40_terminator
- 1.0
-
-
-
-
-
- CD23_wiredProtein
- 1.0
-
-
CD28_cds
@@ -1140,58 +1192,6 @@
-
-
- CD19_norTU
- 1.0
-
-
-
-
-
- C11_part
- 1.0
-
-
-
-
-
-
-
- C12_part
- 1.0
-
-
-
-
-
-
-
- C9_part
- 1.0
-
-
-
-
-
-
-
- C13_part
- 1.0
-
-
-
-
-
-
-
- C10_part
- 1.0
-
-
-
-
-
CD25_promoter
diff --git a/synthesis/src/test/resources/outputFiles/counter.lpn b/synthesis/src/test/resources/outputFiles/counter.lpn
index b45cad939..c32f6fa95 100644
--- a/synthesis/src/test/resources/outputFiles/counter.lpn
+++ b/synthesis/src/test/resources/outputFiles/counter.lpn
@@ -1,9 +1,9 @@
.inputs req
-.outputs
-.internal ack counter_instance__ack b0 a0 b1 a1 counter_instance__a1 counter_instance__state0 counter_instance__state1 counter_instance__a0 counter_instance__b1 counter_instance__b0
+.outputs a1 ack b0 a0 b1
+.internal counter_instance__state0 counter_instance__state1
.dummy counter_instance__T5 counter_instance__T4 counter_instance__T7 counter_instance__T6 counter_instance__T9 counter_instance__assign_10 counter_instance__T8 counter_instance__assign_13 counter_instance__assign_14 counter_instance__assign_11 counter_instance__assign_12 counter_instance__T1 counter_instance__assign_17 counter_instance__T0 counter_instance__assign_18 counter_instance__T3 counter_instance__assign_15 counter_instance__wait_1 counter_instance__wait_0 counter_instance__T2 counter_instance__assign_16 assign_0 assign_1 delay_0 delay_1 delay_2 delay_3 counter_instance__delay_12 counter_instance__delay_11 counter_instance__assign_9 counter_instance__delay_14 counter_instance__assign_8 counter_instance__delay_13 counter_instance__assign_20 counter_instance__delay_10 counter_instance__delay_19 counter_instance__delay_16 counter_instance__delay_15 counter_instance__delay_18 counter_instance__delay_17 counter_instance__assign_19 counter_instance__T26 counter_instance__T20 counter_instance__T21 counter_instance__T22 counter_instance__T23 counter_instance__T24 counter_instance__T25 counter_instance__delay_3 counter_instance__delay_2 counter_instance__delay_1 counter_instance__delay_0 counter_instance__assign_3 counter_instance__T15 counter_instance__assign_2 counter_instance__T16 counter_instance__assign_1 counter_instance__T17 counter_instance__assign_0 counter_instance__T18 T0 counter_instance__assign_7 counter_instance__T19 counter_instance__assign_6 counter_instance__assign_5 counter_instance__assign_4 counter_instance__T10 counter_instance__T11 counter_instance__T12 counter_instance__T13 counter_instance__T14 counter_instance__if_1 counter_instance__delay_7 counter_instance__if_0 counter_instance__delay_6 counter_instance__wait_2 counter_instance__delay_5 counter_instance__delay_4 counter_instance__delay_9 counter_instance__delay_8 counter_instance__if_9 counter_instance__if_12 counter_instance__if_8 counter_instance__if_11 counter_instance__if_7 counter_instance__if_10 counter_instance__if_6 counter_instance__if_5 counter_instance__if_4 counter_instance__if_15 wait_1 counter_instance__if_3 counter_instance__if_14 wait_0 counter_instance__if_2 counter_instance__if_13
#|.places counter_instance__P1 counter_instance__P44 counter_instance__P0 counter_instance__P45 counter_instance__P3 counter_instance__P46 counter_instance__P2 counter_instance__P47 counter_instance__P5 counter_instance__P48 counter_instance__P4 counter_instance__P49 counter_instance__P7 counter_instance__P6 counter_instance__P40 counter_instance__P41 counter_instance__P42 counter_instance__P43 counter_instance__P33 counter_instance__P34 counter_instance__P35 counter_instance__P36 counter_instance__P37 counter_instance__P38 counter_instance__P39 counter_instance__P70 counter_instance__P30 counter_instance__P31 counter_instance__P32 counter_instance__P22 counter_instance__P66 counter_instance__P23 counter_instance__P67 counter_instance__P24 counter_instance__P68 counter_instance__P25 counter_instance__P69 counter_instance__P26 counter_instance__P27 counter_instance__P28 counter_instance__P29 counter_instance__P60 counter_instance__P61 counter_instance__P62 counter_instance__P63 counter_instance__P20 counter_instance__P64 counter_instance__P21 counter_instance__P65 counter_instance__P19 P0 counter_instance__P11 counter_instance__P55 P1 counter_instance__P12 counter_instance__P56 P2 counter_instance__P13 counter_instance__P57 P3 counter_instance__P14 counter_instance__P58 P4 counter_instance__P15 counter_instance__P59 P5 counter_instance__P16 P6 counter_instance__P17 P7 counter_instance__P18 P8 counter_instance__P50 counter_instance__P51 counter_instance__P52 counter_instance__P53 counter_instance__P10 counter_instance__P54 counter_instance__P9 counter_instance__P8
-#@.init_state [0000000000000]
+#@.init_state [00000000]
.graph
counter_instance__P36 counter_instance__T5
counter_instance__T5 counter_instance__P34
@@ -198,8 +198,8 @@ counter_instance__if_2 counter_instance__P18
counter_instance__P53 counter_instance__if_13
counter_instance__if_13 counter_instance__P58
.marking {counter_instance__P0 P0 }
-#@.enablings {}
+#@.enablings {